1. Field of the Invention
The present invention relates to computer systems, and more particularly to a portable computer system that changes system clock speed when entering into battery power mode or entering alternating current mode.
2. Description of the Related Art
In the field of electronic computing, portable computers have attained widespread use. Their small size and transportability make them an invaluable tool to today""s on the go individual. Faster CPUs with denser circuits are continually introduced into portable computers providing greater computing ability. These new CPUs, however, require greater energy resources from portable computer batteries. Added or enhanced features such as sound, graphics, and data drives such as digital video disks (DVD), further require additional battery power. More sophisticated software applications may also indirectly require a greater battery drain. Portable computer owners can avoid the worry of energy drain by simply plugging their machines into an alternating current (AC) outlet, however, this defeats the mobility advantage of a portable computer. In many instances there is no outlet to make use of. An alternate solution is to have a backup battery, but an extra battery takes up space and requires that the user assure that it is always properly charged.
To some degree batteries have also improved. Today""s batteries provide a greater charge life than their predecessors. Computing capability, namely CPU speeds, seems to always improve faster than battery technology. There is always the need to increase battery life, to extend the period of time required to recharge a battery, and to ultimately provide greater portable use to a portable computer user.
For certain applications such as word processing or spreadsheet programs, the system does not need to run at full performance, especially when the system is under battery power. For demanding applications, applications such as interactive gaming, full performance may be required regardless of whether the system is using AC or battery power.
To make use of the times when a system does not need to be at full performance and to extend the life of a battery, it has been found that a CPU can be operated at a lower clock speed when operating on direct current (battery). The system then is switched over to xe2x80x9cperformancexe2x80x9d mode using a higher clock speed when the computer is operated on AC. Such an approach has been implemented by the Intel(copyright) Corporation in its Speedstep(trademark) technology.
When working on battery, a portable PC with Speedstep(trademark) technology automatically detects the change and drops both the CPU clock frequency and voltage. A CPU with Speedstep(trademark) technology can be switched between two performance modesxe2x80x94maximum performance and battery-optimized performancexe2x80x94either automatically or by user command. By default, a portable PC with Speedstep(trademark) technology detects when it is plugged into or unplugged from an AC outlet. When the portable PC is unplugged, the CPU core clock frequency drops to 500 MHz from the peak frequency of 600 MHz or 650 MHz. At the same time, the operating voltage of the CPU drops to 1.35 volts from 1.6 volts. When the portable PC is plugged back into an outlet, the CPU goes back up to peak frequency and increases voltage to 1.6 volts.
Users can also manually adjust the Speedstep(trademark) technology mode operation by accessing an applet, the applet typically appearing as an icon on a Microsoft(copyright) Windows(copyright) taskbar. For example if the user wants increased performance, although the system is running on battery and low performance mode, the user can go to high performance by initiating the applet and forcing the CPU to go to high performance mode.
It has been found that Speedstep(trademark) technology can reduce the active power of the CPU up to 45% while maintaining up to 80% of the maximum performance. Switching voltage levels provides significant power savings, because power consumption occurs in proportion to the square of voltage. In addition reduction in clock frequency also reduces power consumption. Clock frequency has a linear relationship with power consumption. The reduction in power consumption by reducing the clock frequency is not as dramatic as a reduction in voltage, but there is still considerable power savings.
Now referring to FIG. 1, which depicts the prior art Speedstep(trademark) technology. A Speedstep(trademark) transition request may be initiated by a device or application and routed through the Super I/O Controller. The computer""s Operating System (OS) is made aware of such a request and the transition request is made. The OS recognizes that the PC""s power source is being switched from battery to AC, or from AC to battery. The request may also be due to initiating the Speedstep(trademark) applet.
As the Speedstep(trademark) transition request is made, the OS conducts normal system or house keeping processes, then the OS transfers control to a Speedstep(trademark) driver. The Super I/O Controller 10 passes Speedstep(trademark) driver transition protocols by a bus to a South Bridge application specific integrated circuit (ASIC) controller 20. The Speedstep(trademark) driver transition protocols are coordinated between the South Bridge ASIC 20 and an Intel (copyright) (Geyserville (trademark) ASIC 40 through an interface 22.
The Speedstep(trademark) driver then commands the South Bridge ASIC 20 to put the Speedstep(trademark) CPU 70 into a deep sleep, also known as a C3, state. The C3 state is one of four power states, the other three being C0, C1, and C2, defined by the Advance Configuration and Power Interface (ACPI) Specification. The ACPI Specification has been adopted by various CPU manufacturers and other parties in the computing industry. The ACPI Specification power states, in particular, addresses the condition(s) that a CPU is in while in a specific state, in particular power consumption and thermal management conditions. While in the C3 state, the CPU""s caches maintain state but ignore any snoops (inquiries). The operating software is responsible for ensuring that the caches maintain coherency. It has been found that while the Speedstep(trademark) CPU 70 is in C3 state, frequency transition and voltage transition can be optimally changed. Duties of the Speedstep(trademark) CPU 70 are greatly reduced while in the C3 state. For example while in the C3 state, other chipset hardware will maintain CPU cache coherency since the Speedstep(trademark) CPU 70 while in C3 is unable to support this function.
During C3 state, the SDRAM Memory 90 enters a self refresh mode to maintain content. The SDRAM Memory 90 is connected by memory bus 95 to the North Bridge ASIC 30. A memory clock signal 80 is sent to the SDRAM Memory 90 from the Memory Clock Buffer 80. While in C3 state, the memory clock signal 80 is stopped, along with any other clocks that may go to the Speedstep(trademark) CPU 70 and the North Bridge ASIC 30.
Once the Speedstep(trademark) CPU 70 is in C3 state, the Geyserville(trademark) ASIC 40 provides a voltage hi/lo instruction 55 to the CPU Power Supply 60. The CPU Core Voltage 110 supplied by CPU Power Supply 60 is then adjusted according to the performance mode of the Speedstep(trademark) transition, a higher voltage for high performance and a lower voltage for low performance.
In addition, while the Speedstep(trademark) CPU 70 is in C3 state, Geyserville(trademark) ASIC 40 notifies the North Bridge ASIC 30 and the Speedstep(trademark) CPU 70 that the performance mode will change. The Geyserville(trademark) ASIC 40 interfaces with the North Bridge ASIC 30 through South Bridge ASIC 20. South Bridge ASIC 20 in turn communicates to North Bridge ASIC 30 by peripheral component interconnect (PCI) Bus 25. South Bridge ASIC 20 primarily controls PCI Devices, such as PCI Device 110 and PCI Device 120 along the PCI Bus 25. The PCI bus will always run at a clock frequency of 33 MHz. The 33 MHz clock frequency is inherent to the PCI bus.
Control information is passed by South Bridge ASIC 20 to the North Bridge ASIC 30, the North Bridge ASIC 30 in turn passes the information to the Speedstep(trademark) CPU 70 by the Front Side Bus (FSB) 105. The FSB 105 typically and continually maintains a clock speed of 100 MHz. This FSB 105 bus frequency of 100 MHz is also the same frequency as that is on the memory bus frequency 95. The North Bridge ASIC 30 is the primary interface to the Speedstep(trademark) CPU 70. Any memory clock signals 75 that may be sent to Memory Clock Buffer 80 are passed by the North Bridge ASIC 30.
In the case of a battery to AC transition, the Speedstep(trademark) CPU 70 is transitioned to a higher clock frequency, 600 or 650 MHz, and is provided with a higher core voltage. When an AC to battery transition takes place, the Speedstep(trademark) CPU 70 is transitioned to a lower clock frequency, 500 MHz, and is provided with a lower core voltage. The clock frequency is determined by a multiple found and set in the Speedstep(trademark) CPU 70. The multiple, either approximately six (6) for high performance or five (5) for low performance is multiplied by the clock frequency of the FSB 105. Since the FSB 105 always operates at 100 MHz, high performance mode translates to six times 100 MHz or 600 MHz. Likewise, low performance is five times 100 MHz or 500 MHz.
Essentially, with current Intel (copyright)) Speedstep(trademark) technology, only the Speedstep(trademark) CPU 70 frequency is reduced. During the operation of many applications, the Speedstep(trademark) CPU 70 is idling and not requiring high performance. To further save battery power, it would be desirable to reduce further the clock frequency of the Speedstep(trademark) CPU 70 or similar processor. In addition it would be desirable to reduce the clock frequency of the busses interconnecting the various components of the system.
Accordingly, the object of the present invention is to reduce system clock speed on a portable computer system and allowing battery life to be extended when operating on battery power, and increasing clock speed to make use of optimum performance when operating on AC power.
Briefly described, the invention contemplates providing instructions to ASICs to provide transitional signals to a clock generator, CPU power supply, and operational busses to operate at a lower frequency. The invention makes use of the deep sleep transitional state when busses, the CPU, and other devices are functionally operating. Changes are made during the state transition to accommodate for the proper frequency; low frequency for battery power and high frequency for AC power.